The present invention is related to laser-based fuse layouts for semiconductor devices, and more particularly to a circuit and method for minimizing the area of such layouts for use in column address repair in integrated circuit memories.
In general, laser-based fuse layouts in semi-conductor devices are wasteful in terms of the area needed for the fuses. They often require large openings in which no other metal lines can run above or below the fuses. Additionally, no logic gates can be underneath the fuses either. These rules make it difficult to provide both data output logic and column address repair (in a DRAM column circuit) without impacting the area of the chip.
Previous fuse circuit solutions used a fuse load shift register in series with a fuse store shift register. The shifting stops when a counter circuit has counted up to the number of fuses (wherein “n” is used to reference the number of fuses).
While this prior art scheme is simple, it has some major disadvantages. The counter must count exactly the number of fuses that need to be shifted. This means that the number of counter bits required is determined by the following equation:
  m  =            ln      ⁡              (        n        )                    ln      ⁡              (        2        )            
Where n is the number of fuses and m is the number of counter bits. Counters are easiest to deal with when “n” is a power of two and can be rather difficult to implement for when “n” is not a power of two. It becomes difficult for designers to continually change the programming of the counter due to changing column address fields and/or changing the number of column repair fuses.
Referring now to FIG. 1, a portion 100 of a prior art integrated circuit memory is shown having a typical column address repair circuit. The portion 100 of the integrated circuit memory includes a memory array 102, a column decoder block including a plurality of fuses 104, a plurality of “real” column address decoder circuits 108, and a plurality of “spare” column address decoder circuits 106. Note that in FIG. 1, the column repair fuses 104 are located inside the column decoder block itself.
A prior art fuse block 200 is shown in greater detail in FIG. 2, wherein a plurality of fuses is shown having a plurality of first ends available for interrogation and a second common connection usually tied to ground or to a common reference voltage. The column repair fuse block 200 undesirably consumes a great deal of integrated circuit area because no interconnect metal or logic gates can be placed above or below the fuses themselves. Interconnect metal or logic gates can only be placed around the periphery of the fuse block, as is shown in FIG. 2.
A variation of the standard column address repair circuit is shown in FIG. 3. In the integrated circuit memory portion 300 shown in FIG. 3, the actual column repair fuse block 304 is moved from the left side of the memory array 302 and moved to the “top” of the memory array 302. The spare 306 and real 308 column address circuitry remains along the left side of the memory array 302, similar to the circuit shown in FIG. 1. The column repair fuses 304 are replaced in their original location by a plurality of fuse value latches 310. In this way, the fuses can be placed anywhere within the integrated circuit memory and their information can be transferred to the plurality of fuse value latches 310. This affords greater flexibility in laying out the integrated circuit memory, as well as other advantages noted below.
A fuse value latch block 400 is shown in prior art FIG. 4. Fuse value latch block 400 includes individual latches 402 and an output inverter 404. In the fuse value latch block 400, interconnect metal can be placed on top of the block 400, and other logic gates can share any unused area within the block 400. Again, this is a design advantage over the circuit shown in FIG. 1.
The straightforward counting method and state diagram 500 thereof for the repair circuit of the prior art is shown in FIG. 5. At step 502, the counting method enters the shift mode. At step 504 all registers are reset and the fuses are interrogated. At step 506 the bits in the registers are shifted once, and a counter is incremented. At step 508, the counter is interrogated to determine if it has counted “n” times, wherein “n” is the total number of items to be shifted. In the state diagram 500 of FIG. 5, “n” can be any number, and the counter must count exactly to that number. At step 510, shifting stops and the shift mode is exited.
A block diagram of a repair circuit 600 associated with the state diagram of FIG. 5 is shown in FIG. 6. The repair circuit 600 includes a fuse block 602, a fuse load register 604, and a fuse store register 606. The shift output of fuse load register 604 is coupled to the shift input of fuse store register 606. Referring to FIG. 6, it takes “n” shifts to move position “A” to position “S” and position “H” to position “Z”. The straightforward counting method means that the counter has to count exactly to the number “n”. Counting to any number other than “n” will result in the fuse values not being loaded into the proper position in store register 606.
A detailed block diagram of a prior art repair circuit 700 includes a controller 702, an oscillator 704, a fuse load register 706, a fuse store register 708, downstream logic 710, a counter 712, and a decoder 714. The only inputs to this system shown in FIG. 7 are START and NF<0:n−1>, the latter of which is the logical representation of the corresponding fuses. The NF<0:n−1> bits are shifted into the corresponding store registers, FZ<0:n−1>, respectively. This function is complete (meaning NF<0> has shifted all the way to position FZ<0>) when counter 712 as counted up to “n”. Asserting START causes RESET to fire, followed by the firing of SET. Then shifting is enabled and occurs based on the signal INC.
Fuse load register 706 is shown in greater detail in FIG. 8, and includes coupled registers 802, 804, 806, and 808. NF<x> is the logical representation of the status of the corresponding physical fuse, where “x” is a value between 0 and n−1. Fuse store register 708 is shown in greater detail in FIG. 9, and includes coupled registers 902, 904, 906, and 908. Store register 708 does not have any physical fuses connecting to the registers. Nodes FZ<0:n−1> are sent to downstream logic 710 shown in FIG. 7.
What is desired is a fuse-based column address repair circuit for an integrated circuit memory free from the constraints of prior art circuits, including the requirement for counting to an arbitrary number of fuses that is not a power of two.